In recent years, for the transfer of digital data between devices, there has been an increasing demand for serial transfer at higher speeds. Serial transfer of digital data has advantages over parallel transfer of digital data, such as the ability to reduce wires between devices as much as possible, thus allowing for a reduction in size of the wiring cables and connectors, and the ability to reduce crosstalk, or the like, due to interference between wires.
Typically, in serial transfer of digital data, the transmitter unit side converts input parallel digital data to serial digital data and transmits the converted data to the receiver unit. The receiver unit recovers parallel digital data from the received serial digital data.
Referring to FIG. 65, FIG. 65 shows a system configuration of a serial data transfer system in which parallel digital data is serialized and transferred. With any of (1) electrical/DC coupling, (2) electrical/AC coupling and (3) optical coupling, parallel data input to a transmitter unit is encoded by an encoder in a predetermined scheme, converted to serial data by a serializer, amplified, and then transferred. The serial data received by the receiver unit is amplified, converted to parallel data by a CDRPLL circuit, and then decoded by a decoder. DC coupling is advantageous in that it is easy and it is possible to transfer low frequency components including DC components, whereas AC coupling is advantageous in that the transmitter side and the receiver side can be isolated DC-wise from each other. Optical communications systems are advantageous in that they allow for high-speed, long-distance transfer.
In any of these cases, the transmitter unit side and the receiver unit side each perform a recovery operation while individually achieving synchronism. If the degree of synchronism falls out of a certain range, it is no longer possible to recover accurate digital data. Therefore, if synchronism is lost, it is necessary to readjust synchronism. Patent Document 1 describes a clock data recovery circuit as follows. If synchronism is lost, the clock data recovery circuit sends a request signal to transmit a reference clock in a common mode to the transmitter side. As the requested reference clock is received, the clock data recovery circuit in the receiver side switches the mode of operation from a phase comparison mode to a frequency comparison mode and readjusts synchronism.
In an active matrix liquid crystal display or a plasma display, digital data is serially transferred (see, for example, Patent Document 1). The conventional serial transfer operation will now be described with reference to FIG. 66 and FIG. 67.
Image data used in an active matrix liquid crystal display includes RGB color data Rx, Gx and Bx, and synchronization data including DE (DATA ENABLE), Hsync (horizontal synchronization data) and Vsync (vertical synchronization data), as shown in FIG. 66. The source of the image data outputs color data during active periods and synchronization data during blanking periods. Note that Hsync and Vsync stay unchanged at “high” during active periods, i.e., while DE=“Hi”.
FIG. 67 shows an outline of a method for encoding m-bit image data into n-bit data in a digital data serial transfer technique disclosed in Patent Document 2. In this conventional encoding method, m-bit image data is encoded differently in a case where synchronization data is not transmitted (FIG. 67(A)) and in a case where synchronization data is transmitted (FIG. 67(B)).
With the conventional encoding method, in a case where synchronization data is not transmitted (FIG. 67(A)), m-bit image data of each pixel is converted (encoded) into n-bit serial image data in which the same logical bit does not repeat consecutively over k times, and the obtained data is transmitted while being time-division-multiplexed. In a case where synchronization data is transmitted (FIG. 67(B)), m-bit image data of each pixel is time-division-multiplexed and converted to serial image data by adding an (n-m)-bit serial code including an identification bit string in which the same logical bit repeats consecutively k times, and the obtained data is transmitted while being time-division-multiplexed. Herein, m, n and k satisfy the relationship m<n and k<(n-m). In this way, input parallel image data and synchronization data can be transmitted/received over a single channel without interrupting the transmission/reception operation.
[Patent Document 1] U.S. Pat. No. 6,069,927
[Patent Document 2] Japanese Laid-Open Patent Publication No. H9-168147